16 March 2016 – For more than a decade, a staple of Intel’s defense of Moore’s Law has been a development methodology known as “Tick-Tock,” but it’s had its day.
The news emerged in an almost-unnoticed 10-K filing from earlier this month, submitted by Chipzilla to US financial watchdog the SEC.
Here’s how the tick-tock works: Intel first shrinks the architecture of its processor chips to a new process size (those products are the tick) and then it rolls out a new microarchitecture using that process size (those products are the tock). There’s usually a 12 to 18-month gap between the ticks and tocks.
Sadly, shrinking chips down to 10nm feature sizes has proved rather tricky: last year, Intel admitted that the 10nm Cannonlake processor project (the next tick) had to be pushed out to 2017, and it would extend the life of its 14nm Skylake (the previous tock) with a 14nm Kaby Lake (neither a tock or a tick).
That signaled the end times for the tick-tock method, and the 10-K filing confirms it.
Since process sizes are going to have a longer life now, because 10nm is going to be really hard to beat, the development methodology is going to change from a two-step to a waltz, with an “optimisation” step is added after the process and architecture changes. From the filing:
We expect to lengthen the amount of time we will utilise our 14nm and our next-generation 10nm process technologies, further optimising our products and process technologies while meeting the yearly market cadence for product introductions.
Our R&D efforts are intended to enable new levels of performance and address areas such as energy efficiency, system-level integration, security, scalability for multi-core architectures, system manageability, and ease of use.
